Under guidance of Prof

Under guidance of Prof. Anshul Kumar
CS212 - Computer Architecture

Developed by:

Ashish Gupta 98131
Angshuman Parashar 98123

Click here to see the description of Assignment

Description of the project

The Simulator and Assembler was developed in Visual C++ which implements a partial implementation of the SUN-SPARC processor with a pipelined architecture.

Easy to use interactive GUI interface on Windows Platform for easy operation
It implements a two pass assembler to assemble the given SPARC code into machine code.
It is not just a simple instruction execution simulation but the exact simulation of the various components of the actual processor along with timing simulation which tracks the timing of various events and lets you test the architecture under different clock cycle lengths.
Displays the status of various components of the processor like registers , memory etc. using dialog windows for understanding the inner working of the processor.
Various stepping options for the running of the processor. Can run in steps of nanosecond, single cycle or multiple cycles ( Fast Forward ).
Allows for configuration of clock length to test the architecture under various clock lengths ( Useful in determining the minimum clock length required for correctness )
It best serves as a learning tool for understanding the working of a pipelined processor using simulation of simple programs illustrating the main concepts involved in the architecture of the processor.

The above program can be used to gain some insight into making simulations of discrete nature where lots of components are interacting together like to above simulator.

Sparc Info

SPARC Instruction Set implemented in this Simulator

Brief Description of Architecture of SPARC and Instruction Format

Screenshots

The below screenshot shows the main environment of the Sparc Simulator consisting of a text window for adding code and various other dialogs for showing the inner working of the processor.

Dialog Windows

Shows number of clock cycles executed till now

Shows the contents of the instruction memory of the processor

Shows the contents of the registers of the processor ( from 0 to 31 )

Shows the contents of the data memory of the processor ,in binary as well as character format ( for text data )

Shows the contents of the various pipleline registers of the processor to understand the low level working of the processor

Shows the various events pending in the event manager , if the processor is executed in steps of a nanosecond instead of a complete clock cycle. This is possible only because of the timing simulation implemented in the Simulator.

ToolBar Help

Configurable Parameters

Examples

Note: The simulator was developed in a very short time and is not free of bugs. Very long programs will be assembled but may not be executed correctly be the simulator. However , the following examples provided nicely illustrate the working of the processor and its various components like instruction fetch , pipelining, hazard unit , forwarding unit, branching etc.

Examples you can run:

more to come...

examples.zip Contains more examples to try out ( 2k )

Source Code and Windows Executable

SparcSim_Source.zip Source Code for SparcSim. Compiles in Visual C++ 5.0 and above. ( 120k )

SparcSim.exe Executable for SparcSim for Windows Platform ( 151k )

CS212 Links

radix_converter.s Program in MIPS Assembly to convert a number from one radix to another. Includes C++ code for the same. Useful for learning MIPS Assembly.