Simone Campanoni

Associate professor
Department of Computer Science at Northwestern University

Simone Campanoni

Computer Science
Northwestern University

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Publications

Publications


Memory-Centric Compilation

Compilers for general-purpose programming languages (e.g., C/C++) have treated computation as the primary driver of performance improvements in programs, leaving memory optimizations as a secondary consideration. Our goal is to enable the next-generation compilers to optimize program's memory like today's compilers do for computation.


Selected publications

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Parallelizing compilers for shared-memory multicores

The multicore revolution in microprocessor architecture has left most programs behind. A program that maps easily to multicore architectures is the exception, not the rule. Our goal is to map virtually all programs to a multicore platform gaining unprecedented performance.


Selected publications

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Xiaochun Zhang, Timothy M. Jones , and Simone Campanoni
Quantifying the Semantic Gap Between Serial and Parallel Programming
International Symposium on Workload Characterization (IISWC), 2021
Acceptance rate: 39.6% (19/48)
PDF BibTeX IEEE Video
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Simone Campanoni , Kevin Brownell , Svilen Kanev , Timothy M. Jones , Gu-Yeon Wei , and David M. Brooks
Automatically Accelerating Non-Numerical Programs By Extracting Threads with an Architecture-Compiler Co-Design
Communication ACM Research Highlights (CACM), 2017
PDF BibTeX CACM ACM
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Niall Murphy, Timothy M. Jones , Robert Mullins , and Simone Campanoni
Performance Implications of Transient Loop-Carried Data Dependences in Automatically Parallelized Loops
International Conference on Compiler Construction (CC), 2016
Acceptance rate: 31.2% (24/77)
PDF BibTeX ACM
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Simone Campanoni , Glenn Holloway , Gu-Yeon Wei , and David M. Brooks
HELIX-UP: Relaxing Program Semantics to Unleash Parallelization
International Symposium on Code Generation and Optimization (CGO), 2015
Acceptance rate: 27.3% (24/88)
PDF BibTeX ACM IEEE
One of four papers nominated for the Best Paper Award by the Program Committee
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Simone Campanoni , Kevin Brownell , Svilen Kanev , Timothy M. Jones , Gu-Yeon Wei , and David M. Brooks
HELIX-RC: An Architecture-Compiler Co-Design for Automatic Parallelization of Irregular Programs
International Symposium on Computer Architecture (ISCA), 2014
Acceptance rate: 17.8% (46/258)
PDF BibTeX ACM IEEE
IEEE Micro’s Top Picks in Computer Architecture Conferences honorable mention, 2014 IEEE
Communication ACM Research Highlights (CACM), 2017 CACM
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Other publications

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Alessandro A. Nacci, Gianluca C. Durelli, Josue Pagan, Marina Zapater, Matteo Ferroni, Riccardo Cattaneo, Monica Vallejo, Simone Campanoni , Jose Ayala, and Marco D. Santambrogio
Power-Awareness and Smart-Resource Management in Embedded Computing Systems
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2015
PDF BibTeX ACM IEEE
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Khalid Al-Hawaj, Simone Campanoni , Gu-Yeon Wei , and David M. Brooks
Unified Cache: A Case for Low Latency Communication
International Workshop on Parallelism in Mobile Platforms (PRISM), 2015
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Niall Murphy, Timothy M. Jones , Simone Campanoni , and Robert Mullins
Limits of Static Dependence Analysis for Automatic Parallelization
International Workshop on Compilers for Parallel Computing (CPC), 2015
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Simone Campanoni , Svilen Kanev , Kevin Brownell , Gu-Yeon Wei , and David M. Brooks
Breaking Cyclic-Multithreading Parallelization with XML Parsing
International Workshop on Parallelism in Mobile Platforms (PRISM), 2014
PDF
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MARC: Mining Advantages in non-deteRministic Code

The application landscape is rapidly evolving including more often non-deterministic (e.g., randomized) algorithms. Current compilers ignore whether or not a program being compiled is randomized, leaving important opportunities unexplored. The MARC research project aims to identify and exploit such opportunities.


Selected publications

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Ettore M. G. Trainiti, Thanapon Noraset , David Demeter, Doug Downey , and Simone Campanoni
CODE: Compiler-Based Neuron-Aware Ensemble Training
Machine Learning and Systems (MLSys), 2021
Acceptance rate: 24.1% (52/216)
PDF BibTeX
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Michael Leonard , and Simone Campanoni
Introducing the Pseudorandom Value Generator Selection in the Compilation Toolchain
International Symposium on Code Generation and Optimization (CGO), 2020
Acceptance rate: 27.4% (26/95)
PDF BibTeX ACM
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Enrico Armenio Deiana , and Simone Campanoni
Workload Characterization of Nondeterministic Programs Parallelized by STATS
International Symposium on Performance Analysis of Systems and Software (ISPASS), 2019
Acceptance rate: 29.5% (26/88)
PDF BibTeX IEEE
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Other publications

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Ettore M. G. Trainiti, Simone Campanoni , and Doug Downey
Compiler-based neuron-aware deep neural network ensemble training
US Patents, 2022
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Compilers for Sub-Cycle Microarchitecture Activities

Safety margins in conventional architectures are conservative to always avoid computational errors leading to energy inefficiencies. Resilient architectures squeeze these margins to save energy, correcting errors through costly rollback. Co-designed compilers can help resilient architectures to reduce their overhead by adapting the running code to their run-time characteristics


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Yuanbo Fan , Tianyu Jia , Jie Gu , Simone Campanoni , and Russ Joseph
Compiler-guided instruction-level clock scheduling for timing speculative processors
Design Automation Conference (DAC), 2018
Acceptance rate: 24.3% (168/691)
PDF BibTeX ACM
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Vijay Janapa Reddi , Svilen Kanev , Wonyoung Kim , Simone Campanoni , Michael D. Smith , Gu-Yeon Wei , and David M. Brooks
Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-guided Thread Scheduling
International Symposium on Microarchitecture (MICRO), 2010
Acceptance rate: 18.1% (45/248)
PDF BibTeX ACM IEEE
IEEE Micro’s Top Picks in Computer Architecture Conferences, 2011 IEEE
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Vijay Janapa Reddi , Simone Campanoni , Meeta S. Gupta , Michael D. Smith , Gu-Yeon Wei , and David M. Brooks
Software-Assisted Hardware Reliability: Abstracting Circuit-level Challenges to the Software Stack
Design Automation Conference (DAC), 2009
Acceptance rate: 21.7% (148/682)
PDF BibTeX ACM IEEE

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The power of modern compilers for the hardware-software stack

Modern compilers are more powerful than what they are currently used for. This research direction shows how modern compilers create opportunities to reconsider the abstractions used between the layers of the hardware-software stack. Changing such abstractions generates important benefits compared to how we have been designing systems.


Selected publications

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Ling Jin, Yinzhi Cao , Yan Chen , Di Zhang, and Simone Campanoni
EXGEN: Cross-platform, Automated Exploit Generation for Smart Contract Vulnerabilities
IEEE Transactions on Dependable and Secure Computing (TDSC), 2023
PDF BibTeX IEEE
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Souradip Ghosh , Michael Cuevas , Simone Campanoni , and Peter Dinda
Compiler-based Timing For Extremely Fine-grain Preemptive Parallelism
High Performance Computing, Networking, Storage and Analysis (SC), 2020
Acceptance rate: 25.1% (95/378)
PDF BibTeX ACM IEEE
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Brian Suchy , Simone Campanoni , Nikos Hardavellas , and Peter Dinda
CARAT: A Case for Virtual Memory through Compiler- And Runtime-based Address Translation
International Conference on Programming Language Design and Implementation (PLDI), 2020
Acceptance rate: 22.6% (77/341)
PDF BibTeX ACM

Other publications

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Others

Here you can find exploratory research we did.


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Ishita Chaturvedi , Bhargav Reddy Godala , Yucan Wu , Ziyang Xu , Konstantinos Iliakis, Panagiotis-Eleftherios Eleftherakis, Sotirios Xydis , Dimitrios Soudris , Tyler Sorensen , Simone Campanoni , Tor M. Aamodt , and David I. August
GhOST: a GPU Out-of-Order Scheduling Technique for stall reduction
International Symposium on Computer Architecture (ISCA), 2024
Acceptance rate: 21.2% (79/372)
Artifact: Available Artifact: Functional Artifact: Reproduced
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Other publications

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Bytecode Virtual Machines

Virtual machines designed to execute bytecode programs are everywhere. The most successful and widely-adopted examples are Java and .NET. Browsers are virtual machines as well thanks to their ability to run programs written in multiple languages (e.g., JavaScript). A bytecode virtual machine usually includes several components. Code generators, code optimizers, garbage collectors, execution engine, and profilers are the most common ones. Understanding interactions of these components allows them to be co-designed, which open interesting optimization opportunities.


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Simone Campanoni
Guide to ILDJIT
Book from Springer, 2011
BibTeX Springer GitHub
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Simone Campanoni , Martino Sykora , Giovanni Agosta , and Stefano Crespi Reghizzi
Dynamic Look Ahead Compilation: a technique to hide JIT compilation latencies in multicore environment
International Conference on Compiler Construction (CC), 2009
Acceptance rate: 25.0% (18/72)
PDF BibTeX ACM Springer GitHub

Other publications

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Simone Campanoni , and Luca Rocchini
Static Memory Management within Bytecode Languages on Multicore Systems
Workshop on Computing in Heterogeneous, Autonomous ’N’ Goal-oriented Environments (CHANGE), 2011
PDF IEEE GitHub
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Simone Campanoni , Giovanni Agosta , and Stefano Crespi Reghizzi
ILDJIT: a Parallel Dynamic Compiler
International Conference on Very Large Scale Integration (VLSI-SoC), 2008
PDF GitHub

Placing wireless sensors

Placing wireless sensors in the target environment is crucial to gain the right knowledge.


Selected publications

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Other publications

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Others

Here you can find research we did in past projects.


Selected publications

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Filippo Sironi , Davide B. Bartolini , Simone Campanoni , Fabio Cancare , Henry Hoffmann , Donatella Sciuto , and Marco D. Santambrogio
Metronome: Operating System Level Performance Management via Self-Adaptive Computing
Design Automation Conference (DAC), 2012
Acceptance rate: 22.7% (168/741)
PDF BibTeX ACM IEEE
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